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Subtraction: How a mining card shows a chipmaker selling the A100's die with capability withheld

A processor was built, then deliberately reduced, then sold at a fraction of its worth to people solving a puzzle that no longer exists. The reduction is the product.

By · r = cos(kθ) · seed k 5/7/3 · NVIDIA CMP 170HX / GA100
Film · YouTube · plays here

Thesis

The most expensive engineering is the engineering that takes things away.

00 · The argument

The margin moved out of the making.

Fabrication is the part everyone photographs. Cleanrooms, lithography, a wafer held up to a light. It is also the part that differentiates fewer and fewer companies, because only a handful can make the smallest transistors, and the machines that print the finest layers come from a single Dutch supplier. [27]

The margin no longer sits in the making. It sits in the permissions. A modern accelerator ships with capability physically present and administratively withheld, and the price of the product is set by how much of itself the buyer is allowed to use. [09]

This is not a claim that requires trust. The evidence is purchasable. When the cryptocurrency market collapsed it stranded a very large number of processors whose only purpose had been to be deliberately worse than their own silicon, and until the summer of 2026 those processors sold used for a few hundred dollars, cheap enough to buy and examine. [10]

What follows is a reading of one such processor. It was chosen because it is the least subtle example available, and because anyone who doubts the reading can buy the evidence and check.

01 · The price of a dead idea

September fifteenth, 2022

Ethereum stopped using proof of work. The network no longer needed anyone to solve anything, and the entire global apparatus assembled to solve it became, within a single day, an inventory problem. [14] [15]

Gaming cards had somewhere to go. Their prices had been falling since January, they fell again in the week after the Merge, and the used ones went to eBay. The world moved on. [16] [33] [34] The purpose-built mining hardware had nowhere. It had no display outputs, no market outside the one that had just closed, and a manufacturer with no incentive to help it find another. [06]

It had gone on sale at roughly $4,300, a retailer’s price; NVIDIA never published one. [07] [08] Until the summer of 2026 it sold used for a few hundred dollars. Then a tool unlocked the memory it had carried all along, and by September it sold on eBay for $1,300 to $1,700. A different industry had worked out what was underneath it. [10] NVIDIA has never published a production figure. It reported $550 million of CMP revenue for fiscal 2022, every model together, so the size of the stranded inventory is estimated rather than known. [08] [10] [13]

The card had been sold at a premium on the explicit promise that it could do one thing well and nothing else at all. When the one thing ended, the promise held, in the main, for nearly four years.

02 · The die

It is the same piece of silicon.

The processor inside the mining card is GA100. It is the processor inside the A100, the accelerator that trained Stable Diffusion and Meta’s first LLaMA models. [01] [05] [29] [30]

GA100 is 826 square millimetres of seven nanometre silicon carrying 54.2 billion transistors. Eight GPU processing clusters. Up to 128 streaming multiprocessors, 8,192 single precision cores and 512 third generation tensor cores. On the A100 they feed a 40 megabyte level two cache. [01]

It cannot show anything. There are no ray tracing cores, no video encoder and no display connectors, because nothing it was designed for involves a screen. It multiplies matrices, the operation at the core of deep learning, and it does so against stacked high bandwidth memory sitting on the same package rather than scattered across a board. [01]

NVIDIA sold the mining card in two versions, 8 gigabytes on four stacks and 10 on five; this edition reads the 8 gigabyte card, which carries the GA100-105F-A1 bin. Seventy of the 128 streaming multiprocessors are active, giving 4,480 single precision cores and 280 tensor cores, clocked at 1140 base and 1410 boost against a 4,096-bit memory interface. That is a harvested die. Nothing about it is remarkable yet. [05] [08] [10] [11]

Same die, different permissions

Two products. One design. The distance between them is not manufacturing. It is configuration, and configuration is written after the wafer is finished.

03 · What was removed

Three cuts, none of them accidents.

The restrictions fall into three categories, and the categories matter more than the numbers, because they are not equally permanent: two are held by firmware alone, and the third is partly cut into the circuit board.

Memory geometry. The firmware reports a smaller pool than the package physically carries. The system believes the card, because the system has no independent way to count. [09] [11]

Compute throughput. Floating point multiply-add is throttled below a graphics card from 2008. The units are present. Multiply-add runs at a thirty-second of its rate. [05] [09]

Host bandwidth. The connection to the motherboard is held at an early generation and a quarter of the standard lane width. This one is elegant, because a training workload that cannot be fed is useless regardless of what the cores are allowed to do. [05]

The figures. Memory reports 8 gigabytes across a 4,096-bit bus rated at 1.49 terabytes per second; measured, it sustains 1.36. [05] Four active stacks of HBM2e, which would make two gigabytes a stack, and the HBM2e SK hynix has mass-produced since 2020 holds sixteen to a stack. [10] [28] The arithmetic is available to anyone who wants to do it. In 2026 someone did it in software, and the card reported sixty four. [10]

Compute is the clearer cut. On paper the enabled cores give 12.63 teraflops of single precision. [08] Measured with fused multiply-add, the instruction nearly all software uses, the card delivers 0.39. Without it, 6.25. [05] The cores are present, clocked and counted. They are simply not permitted to multiply and add in one step.

Host bandwidth sits at PCIe 1.0 by four lanes, against the 4.0 by sixteen the same die runs on an A100. [01] [05]

Several mechanisms hold the cuts in place. The VBIOS is signed. [05] One time programmable fuses carry the limits, and firmware reads them at boot. The lane width is cut on the circuit board itself, where the capacitors for twelve of the sixteen lanes were never fitted. [09] The driver is not one of them: NVIDIA’s own driver runs the card, though it leaves it off its list of supported products. [05] [10] [26] The difference that matters is between a fuse that firmware reads and a fuse that cuts a circuit. In June 2026 a paper showed these were the first kind: compute, memory and one step of the PCIe generation were lifted in software. Only the lanes needed a soldering iron. [09] [10]

A fuse that firmware reads and a fuse that cuts a circuit are the same lock to a customer and entirely different locks to an engineer.

04 · Binning is not this

Salvage asks what still works. Segmentation asks what they will pay.

An 826 square millimetre die is enormous, and at that size perfect yield is not a target anyone holds. A speck of dust lands on a wafer, a few cores die, and the industry response is sensible: disable the broken region and sell the chip as a lesser part. This is binning. It is honest, it is efficient, and it is the reason large processors are economically possible at all.

Binning can explain seventy active multiprocessors out of one hundred and twenty eight. It does not explain a card that reports an eighth of the memory on its package. [10] It does not explain an interconnect held three generations back, with the capacitors for twelve of its sixteen lanes left off the board. [09] Nothing about a lithography defect removes a capacitor from a circuit board.

The distinction is the whole argument. One set of limits describes damage. The other describes a decision, implemented in fuses, firmware and the board, which means someone calculated that it would earn more than it cost.

The test

Ask whether the silicon under the limit still works. If it does, the limit was never damage. It was a price, and burning it into a fuse made it look permanent rather than honest. On this card it was not permanent either.

05 · Older than silicon

Nothing here is new.

IBM shipped mainframes with processors already installed and dormant, switched on by an encrypted configuration record when the customer’s workload grew. The metal arrived on day one. The permission arrived with the order. IBM called it Capacity on Demand and the customers accepted it, because the upgrade needed no new hardware and no outage. [17] [35]

Intel sold a consumer processor in 2010 with cache and threading disabled, and a card on the shop shelf that unlocked them for fifty dollars. The press turned on it within days. It was extended once, in 2011, and then dropped. [18] [19] [20]

Tesla shipped battery packs that were physically larger than the capacity the car would use, unlockable later for a fee. [21] Some manufacturers have tried the same arrangement with seat heaters, which is the version that made newspapers, because a heating element is easy to picture and a memory controller is not. [22] [23] [36]

The mining card belongs to this lineage. What distinguishes it is the absence of the upgrade path. IBM would sell you the key. Intel would sell you the key. Here NVIDIA never sold one, because the entire point was that this customer must never become that customer. In 2026 someone else wrote it. [12]

Every precedent above offered a way to pay for the rest of the machine. This one offered nothing, which is what makes it the purest specimen of the practice rather than the worst.

06 · What was undone

People went looking for the rest of it.

Cards that cheap, a few hundred dollars until the summer of 2026, attract a particular kind of attention. Once the price fell below the cost of caring whether it survived, a community formed around the question of how much of the original processor was still reachable. It is on record from the end of 2023. [31]

What that community recovered is now partly on record. The method is public, in a paper and an open tool. [09] [12] One named test reached 64 gigabytes on an 8 gigabyte card, and sixteen lanes of PCIe 2.0 once the missing capacitors were soldered on. [10] The 10 gigabyte card carries 80 but runs stable only to 40 as the tool sets it; the paper made all 80 stable by refreshing the memory more often, at about a third less throughput. [09] [10] [12] The faster PCIe generations have not been reached. [09] Anyone who tells you the rest is settled is selling something.

The attempt was the finding. People do not spend years attacking firmware to reach hardware that is not there. The effort was evidence before any attempt succeeded. Then one did.

This edition does not publish a procedure. The interesting finding is not how to perform the modification. It is what the modification proves about where the value in the original product was located.

A note on legality

In the United States the governing provision is section 1201 of the Digital Millennium Copyright Act. In Canada it is the technological protection measure provisions added to the Copyright Act by the Copyright Modernization Act. Both carry repair related exceptions, both have widened, and neither settles whether an accelerator you already own sits inside them. The American rule defines repair as a return to the original specification. An unlock goes past it. [24] [25]

This edition describes the locks. It does not open them.

Table 01 · The delta

One die, five permissions.

The same GA100 die in five configurations.
AttributeGA100 full dieA100 40GB PCIeA100 80GB PCIeCMP 170HX 8 GB, lockedCMP 170HX 8 GB, unlocked
ProcessTSMC N7TSMC N7TSMC N7TSMC N7TSMC N7
Die area826 mm²826 mm²826 mm²826 mm²826 mm²
Transistors54.2 B54.2 B54.2 B54.2 B54.2 B
Die binGA100 fullGA100-883AA-A1GA100-893FFGA100-105F-A1GA100-105F-A1
GPCs877n/an/a
Streaming multiprocessors1281081087070
FP32 cores8,1926,9126,9124,4804,480
Tensor cores (3rd gen)512432432280280
L2 cache48 MB40 MB40 MB32 MBn/a
Base / boost clock, MHzn/a765 / 14101065 / 14101140 / 1410n/a / 1410
Memory typeHBM2HBM2HBM2eHBM2eHBM2e
Memory bus6,144-bit5,120-bit5,120-bit4,096-bit4,096-bit
Memory reportedn/a40 GB80 GB8 GB64 GB
Memory physicaln/a40 GB80 GB64 GB64 GB
Bandwidth, ratedn/a1.56 TB/s1.94 TB/s1.49 TB/s1.49 TB/s
FP32 theoreticaln/a19.5 TF19.5 TF12.63 TF12.63 TF
FP32 deliveredn/auncappeduncapped0.39 TF12.2 TF
Host interfacePCIe 4.0 x16PCIe 4.0 x16PCIe 4.0 x16PCIe 1.0 x4PCIe 2.0 x4
Display outputnonenonenonenonenone
Board powern/a250 W300 W250 W250 W
Price at launchn/a£8,299 ex VATn/a~$4,300free tool
Used price, Sep 2026n/a$3,500n/a$1,300 to $1,700same card

FP32 theoretical is cores × 2 × boost clock. FP32 delivered is what the card actually returns: on the locked card with fused multiply-add (6.25 TF without it), on the unlocked card a matrix multiply. The distance between those two rows is the subject of this edition. n/a means no source gives the figure.

GA100 and A100: [01] [02] [03]; the full die’s 48 MB L2 is NVIDIA’s slice count, twelve memory controllers of eight 512 KB slices, and ComputerBase prints it [04]; NVIDIA itself names no full-die clock, so no full-die FP32. A100 delivered: NVIDIA says each card runs unconstrained up to its power limit [02] [03]. CMP locked: [05] [06] [07] [08] [10]; its L2 is the driver’s reading [05], its launch price a Dubai retailer’s, October 2021 [07], its board power the card’s rating as Tom’s Hardware reported it, not NVIDIA’s [07], which the unlock does not change. CMP unlocked: [09] [10] [11] [12]; the die bin and memory bus are the locked card’s, which a software unlock does not touch [05] [08]; its L2 and base clock are driver readings no source took after the unlock, so they read n/a; 12.2 TF was measured on the 10 GB card [09]; x16 needs the missing capacitors soldered on [10]. A100 40GB launch price: a UK retail listing, July 2020 [32]; NVIDIA published none. The used prices are LTT Labs’ eBay sold observations of September 2026 [10]; the A100 80GB has no dated used price.

07 · The licensing surface

A specimen, not a scandal.

The mining card is not a scandal. It is a specimen, and it is valuable precisely because the company that made it had no reason to be subtle. There was no consumer to reassure and no reviewer to satisfy. The segmentation could be implemented openly, which means it can now be read openly.

What it records is a transition that has already happened everywhere else and is simply easier to see here. The physical object arrives complete. The commercial object is assembled afterwards, in firmware, out of decisions about what the buyer has paid to be allowed to do.

The practice is spreading: the difference between a flagship and a cut-down part of the same die is increasingly enforced not by physically different silicon but by fuses and by the firmware that reads them. [09] That moves the lock out of the silicon and into code, which is cheaper to fit and easier to pick. A fuse that only firmware reads differentiates price, not security, and on this card it did not hold. [09]

What the specimen proves

That capability and permission are now separately priced, and only one of them ships in the box.

08 · Sources

Sources

Read on 17 and 18 October 2026

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You do not buy a processor. You buy a list of permissions.

Aedificare · 18 Oct 2026The Subtraction